Field of the Invention
The present invention relates to a method of transmitting data in a wireless access system, and more particularly, to various methods of dividing input data into code blocks in consideration of the size of an error detection code.
Discussion of the Related Art
In transmitting data, data transmission efficiency and reliable data transmission are important. To increase data transmission efficiency, methods of dividing data before transmission and methods using an error detection code to check whether data contains an error are generally used.
Error control refers to a mechanism for detecting and correcting errors generated during data transmission. Error control schemes include an automatic repeat request (ARQ) scheme, a forward error correction (FEC) scheme, and a backward error correction (BEC) scheme.
The ARQ scheme allows, for reliable data transmission on a communication line, a receiving side to check whether an error occurs by means of an acknowledgement (ACK) signal and timeout and allows a transmitting side to retransmit a frame in which an error has occurred. The ARQ scheme, which is called an automatic retransmission request scheme, allows a receiving side to detect an error and to request data retransmission. In the FEC scheme, a transmitting side adds redundancy to characters or frames before transmission and a receiving side detects and corrects errors using the redundancy. The BEC scheme adds redundancy for detecting errors and transmits an ARQ signal for data retransmission to a transmitting side.
Error detection refers to a technique for allowing a receiving side to recognize whether an error has occurred during transmission. An error detection code refers to a code supporting the error detection technique. Error detection techniques include parity check, checksum, cyclic redundancy check (CRC), and weighted code techniques.
Error correction refers to a coding technique including sufficient redundancy in a transmitted data block such that a receiving side can infer transmission characters from the received data block. In terms of an open system interconnection (OSI) layer model, error correction is mainly implemented in a data link layer. Meanwhile, error detection refers to a coding technique in which redundancy is added so that the receiving side can detect the occurrence of an error and make a request for retransmission.
The error correction includes a block code scheme in which a prescribed length of redundancy is added to a predetermined length of information (signal) so that a receiving side can correct errors and a convolutional code scheme in which a coder has a memory to use, during coding, a part of previously input signals in addition to currently input signals.
A block code includes Hamming codes, Reed-Solomon codes as cyclic codes, Bose-Chaudhuri-Hocquenghem (BCH) codes, and cyclic redundancy check (CRC) codes. A convolution code includes Viterbi codes and turbo codes.
The parity check is most generally used when the number of information bits is small and the likelihood of error generation is low. Although the parity check is widely used in asynchronous communication due to simplicity thereof, it is difficult to detect errors when the number of errors is an even number. The parity check includes an odd parity check in which the number of 1's in characters coding parity bits is set to an odd number and an even parity check in which the number of 1's in characters coding parity bits is set to an even number.
The CRC, which is one of error detection methods, refers to a technique in which a transmitting side adds a result extracted by a polynomial from transmitted data to a frame check sequence (FCS) and transmits the attached field and a receiving side check for errors by confirming whether the extracted result is identical with an extracted result performed by the same method in the receiving side. The CRC is powerful and a hardware configuration thereof is simple. A remainder obtained by dividing an original data frame which is to be transmitted by the transmitting side by a CRC generator polynomial is the FCS. The CRC generator polynomial, which is a divisor for division, is needed to generate the FCS. The FCS is attached to an end of the original data frame so that a result frame (adding the FCS to the original data) can be accurately divided by a predefined polynomial. That is, the FCS calculated for the original data frame is attached to an end of the frame. Here, the predefined polynomial is referred to as the divisor or CRC polynomial.
A receiving side performs CRC after receiving the result frame. The receiving side checks a reminder by dividing a received data frame by the same CRC polynomial used during transmission. The receiving side detects errors by checking whether a remainder obtained by dividing data transmitted together with redundancy by original data is 0. If the remainder is not 0, it is determined that an error has occurred during transmission.